When data is transmitted in parallel through data transmission lines having a plurality of signal lines, signal delay is caused by parasitic resistance of each transmission line.
FIG. 1 is a waveform diagram illustrating signal delay according to a plurality of transmission lines.
Referring to FIG. 1, data transmitted according to a clock signal Clock are transmitted through respective transmission lines BUS1, BUS2, BUS3, and BUS4 with predetermined signal delays.
Such signal delays have different values depending on parasitic resistance of the respective transmission lines BUS1, BUS2, BUS3, and BUS4.
When data that are transmitted through the transmission lines BUS1, BUS2, BUS3, and BUS4 are digital signals, since the digital signals are transmitted at a higher speed than, for example, analog signals, the signal delay may cause a data error. As shown in FIG. 1, when data are exchanged in parallel, a time required for loading the data on the transmission lines BUS1, BUS2, BUS3, and BUS4 stably varies according to the transmission lines BUS1, BUS2, BUS3, and BUS4. For this reason, after the data loaded on all of the transmission lines BUS1, BUS2, BUS3, and BUS4 stabilized, logic values are determined based on a synchronizing clock.
Accordingly, when interfacing to a memory is carried out through a programmable logic device (PLD), even if the clock signal for the data transmission lines BUS1, BUS2, BUS3, and BUS4 does not conform to the memory specification, a clock signal having a plurality of cycles must be used to make data stable. This may cause a decrease in memory access speed.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.